Fabrication method of semiconductor structure

ABSTRACT

A fabrication method of a semiconductor structure includes providing a chip having at least an electrode pad, forming a titanium layer on the electrode pad, forming a dielectric layer on the chip and a portion of the titanium layer, forming a copper layer on the dielectric layer and the titanium layer, forming a conductive pillar on the copper layer corresponding in position to the titanium layer, and removing a portion of the copper layer that is not covered by the conductive pillar. When the portion of the copper layer is removed by etching, undercutting of the titanium layer is avoided since the titanium layer is covered by the dielectric layer, thereby providing an improved support for the conductive pillar to increase product reliability.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of copending application U.S. Ser. No.13/167,086, filed on Jun. 23, 2011, which claims under 35 U.S.C. §119(a)the benefit of Taiwanese Application No. 100115712, filed May 5, 2011,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor structures andfabrication methods thereof, and, more particularly, to a semiconductorstructure having conductive pillars and a fabrication method thereof

2. Description of Related Art

Electronic products are becoming lighter, thinner and smaller, as wellas developed for high performance and multi-functionality. There arevarious types of semiconductor chip packages, such as wire bonding typepackages, flip-chip type packages and so on. Compared with wire bondingtype packages, flip-chip type packages are advantageous in reducing theoverall volume of semiconductor devices.

A fabrication method of a flip-chip type package generally involveselectrically connecting an active surface of a chip to conductive padsof a packaging substrate through a plurality of conductive bumps, andfilling an underfill between the active surface of the semiconductorchip and the substrate for encapsulating the conductive bumps. Therein,the material of the conductive bumps greatly affects the flip-chipalignment accuracy.

U.S. Pat. No. 7,863,740 and No. 7,804,173 disclose methods forelectrically connecting a semiconductor chip with a packaging substratethrough copper pillars.

Referring to FIG. 1A, a semiconductor chip 10 having at least anelectrode pad 100 is provided. The outer surface of the semiconductorchip 10 is made of a silicon nitride layer, which has an opening forexposing the electrode pad 100, respectively.

Then, a dielectric layer 12 is formed on the silicon nitride layer 101and around the wall of the opening of the silicon nitride layer 101.Subsequently, a titanium layer 11 is formed to cover the entire surfaceof the dielectric layer 12 and the electrode pad 100. Further, a copperlayer 13 is formed to cover the entire surface of the titanium layer 11.

Referring to FIG. 1B, a resist layer 14 is formed on the copper layer 13and an open area 140 is formed in the resist layer 14 for exposing aportion of the copper layer 13. Then, a copper pillar 15 is formed onthe exposed portion of the copper layer 13 and a solder material 16 isformed on a top surface of the copper pillar 15.

Referring to FIG. 1C, the resist layer 14 is removed to expose a portionof the copper layer 13.

Referring to FIG. 1D, using the copper pillar 15 as an etch stop layer,an etching process is performed to remove the exposed portion of thecopper layer 13 and the titanium layer 11 under the exposed portion ofthe copper layer 13. Thereafter, a solder bump can be formed on thecopper pillar 15 and the solder material 16, and then a reflow processcan be performed so as to form a conductive bump electrically connectingthe chip 10 and a packaging substrate (not shown).

Since the copper pillar 15 does not deform during the reflow process,melting and collapsing of the copper pillar 15 can be prevented, therebyavoiding position deviation of the chip 10 and increasing positionalignment accuracy of the chip 10.

However, since the etching process using an etching solution isisotropic, when the copper layer 13 and the titanium layer 11 under thecopper layer 13 are partially removed by etching, an undercut of thetitanium layer 11 can occur, as shown at position K of FIG. 1D, thusresulting in an insufficient support for the copper pillar 15 andreducing the reliability of the conductive bump.

Therefore, there is a need to provide a semiconductor structure and afabrication method thereof so as to overcome the above-describeddrawback.

SUMMARY OF THE INVENTION

Accordingly, the present invention provides a fabrication method of asemiconductor structure, which comprises the steps of: providing a chiphaving at least an electrode pad; forming a first metal layer on theelectrode pad; forming a dielectric layer on the chip and the firstmetal layer, the dielectric layer having an opening for exposing aportion of the first metal layer; forming a second metal layer on thedielectric layer and the exposed portion of the first metal layer, thematerial of the first metal layer being different from that of thesecond metal layer; forming a conductive pillar on the second metallayer corresponding in position to the first metal layer; and removing aportion of the second metal layer that is not covered by the conductivepillar and preserving the remaining portion of the second metal layercovered by the conductive pillar.

The above-described method forms the first metal layer first and thenforms the dielectric layer so as to define the size of the first metallayer before forming the second metal layer. Therefore, when the secondmetal layer is partially removed by etching, undercutting of the firstmetal layer can be avoided since the first metal layer is covered by thedielectric layer.

According to the above-described method, the present invention furtherprovides a semiconductor structure, which comprises: a chip having atleast an electrode pad; a first metal layer formed on the electrode pad;a dielectric layer formed on the chip and the first metal layer andhaving an opening for exposing a portion of the first metal layer; asecond metal layer formed on the exposed portion of the first metallayer and the dielectric layer therearound, the material of the firstmetal layer being different from that of the second metal layer; and aconductive pillar disposed on the second metal layer.

In another aspect, the present invention provides a fabrication methodof a semiconductor structure, which comprises: providing a chip havingat least an electrode pad; forming a first metal layer on the electrodepad; forming a second metal layer on the first metal layer, the materialof the first metal layer being different from that of the second metallayer; forming a conductive pillar on the second metal layercorresponding in position to the first metal layer, the first metallayer having an area larger than the sectional area of the conductivepillar; and removing a portion of the second metal layer that is notcovered by the conductive pillar and preserving the remaining portion ofthe second metal layer covered by the conductive pillar.

When the second metal layer is partially removed by etching, since thearea of the first metal layer is larger than the sectional area of theconductive pillar, undercutting of the first metal layer can be avoided.That is, instead of completely positioning the titanium layer under acopper pillar as in the prior art, a portion of the first metal layer isexposed from the conductive pillar even if the first metal layerexperiences an isotropic etching process.

According to the above-described method, the present invention providesanother semiconductor structure, which comprises: a chip having at leastan electrode pad; a first metal layer formed on the electrode pad; asecond metal layer formed on the first metal layer, the material of thefirst metal layer being different from that of the second metal layer;and a conductive pillar disposed on the second metal layer, the firstmetal layer having an area larger than the sectional area of theconductive pillar.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A to 1D are cross-sectional views showing a fabrication method ofa semiconductor structure in the prior art;

FIGS. 2A to 2G are cross-sectional views showing a fabrication method ofa semiconductor structure according to a first embodiment of the presentinvention; and

FIGS. 3A to 3D are cross-sectional views showing a fabrication method ofa semiconductor structure according to a second embodiment of thepresent invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The following illustrative embodiments are provided to illustrate thedisclosure of the present invention and its advantages, these and otheradvantages and effects will be apparent to those in the art afterreading this specification.

It should be noted that the drawings are not intended to limit thepresent invention. Various modification and variations can be madewithout departing from the spirit of the present invention. Further,terms such as “one”, “above” and so on are merely for illustrativepurpose and should not be construed to limit the scope of the presentinvention.

First Embodiment

FIGS. 2A to 2G are cross-sectional views showing a fabrication method ofa semiconductor structure according to a first embodiment of the presentinvention.

Referring to FIG. 2A, a semiconductor chip 20 having at least anelectrode pad 200 made of, for example, aluminum is provided. The outersurface of the semiconductor chip 20 is made of, for example, a siliconnitride layer 201 and has an opening for exposing the electrode pad 200.There are various pertinent chip structures in the art and detaileddescription thereof is omitted herein for brevity.

Referring to FIG. 2B(b), a first metal layer 21 a, such as a titaniumlayer or a titanium tungsten layer, is formed on the electrode pad 200and the silicon nitride layer 201 therearound.

In the present embodiment, the first metal layer is formed through apatterning process. First, as shown in FIG. 2B(a), a first metalmaterial 21 is formed on the electrode pad 200 and the entire surface ofthe silicon nitride layer 201 by sputtering. Then, a resist layer 210 isformed to cover a portion of the first metal material 21 located on theelectrode pad 200 and the silicon nitride layer 201 around the electrodepad 200. Referring to FIG. 2B(b), the remaining portion of the firstmetal material 21 that is not covered by the resist layer 210 is removedby etching and then the resist layer 210 is removed to obtain a firstmetal layer 21 a. The resist layer 210 can be made of photoresist, andopen areas of the resist layer 210 for partially exposing the firstmetal material 21 can be formed by exposure and development. It shouldbe noted that various patterning processes in the art can be applied inthe present invention and detailed description thereof is omittedherein.

Referring to FIG. 2C, a dielectric layer 22 is formed on the siliconnitride layer 201 and the first metal layer 21 a and an opening 220 isformed in the dielectric layer 22 for exposing a portion of the firstmetal layer 21 a.

In the present embodiment, the dielectric layer 22 is a polyimide layer,but is not limited thereto.

Referring to FIG. 2D, a second metal layer 23, such as a copper layer,is formed on the dielectric layer 22 and the exposed portion of thefirst metal layer 21 a by sputtering.

Then, a resist layer 24 made of photoresist is formed on the secondmetal layer 23, and an open area 240 is formed in the resist layer 24 byexposure and development for exposing a portion of the second metallayer 23 corresponding in position to the first metal layer 21 a. In thepresent embodiment, the open area 240 is larger than the area of thefirst metal layer 21 a.

Referring to FIG. 2E, a conductive pillar 25 is formed on the secondmetal layer 23 in the open area 240 by electroplating. In the presentembodiment, the conductive pillar 25 is a copper pillar.

Further, a conductive material 26 can be formed on a top surface of theconductive pillar 25. In the present embodiment, the conductive material26 consists of a nickel material 260 and a solder material 261. In otherembodiments, the conductive material 26 can be a solder material.

Referring to FIG. 2F, the resist layer 24 is removed to expose a portionof the second metal layer 23 that is not covered by the conductivepillar 25.

Referring to FIG. 2G, the exposed portion of the second metal layer 23is removed by etching to expose the dielectric layer 22 around theconductive pillar 25. Meanwhile, the remaining portion of the secondmetal layer 23 that is covered by the conductive pillar 25 is preserved.Thus, a semiconductor structure is obtained. In subsequent processes, asolder bump can be formed on the conductive pillar 25 and the soldermaterial 26 and then reflowed so as to form a conductive bumpelectrically connecting the semiconductor structure and a packagingsubstrate (not shown).

The semiconductor structure has a semiconductor chip 20 having at leastan electrode pad 200, a first metal layer 21 a formed on the electrodepad 200 and a surface of the chip 20 around the electrode pad 200, afirst dielectric layer 22 formed on the chip 20 and the first metallayer 21 a and having an opening 220 for exposing a portion of the firstmetal layer 21 a, a second metal layer 23 formed on the exposed portionof the first metal layer 21 a and the dielectric layer 22 therearound,and a conductive pillar 25 disposed on the second metal layer 23.Therein, the material of the first metal layer 21 a (for example,titanium) is different from the material of the second metal layer 23(for example, copper). The semiconductor structure further has aconductive material 26 disposed on a top surface of the conductivepillar 25.

The present invention defines the size of the first metal layer 21 abefore forming the dielectric layer 22 and the second metal layer 23.When the exposed portion of the second metal layer 23 is removed byetching, undercutting of the first metal layer 21 a can be avoided sincethe first metal layer 21 a is covered by the dielectric layer 22,thereby providing sufficient support to the conductive pillar 25 andaccordingly increasing the reliability of the subsequently formedconductive bump.

Second Embodiment

FIGS. 3A to 3D are cross-sectional views showing a fabrication method ofa semiconductor structure according to a second embodiment of thepresent invention. Compared with the first embodiment, the dielectriclayer and the first metal layer of the present embodiment are fabricatedin a different sequence. Related processes are described as follows.

Referring to FIG. 3A, continuing from FIG. 2A, a dielectric layer 22′ isformed on the silicon nitride layer 201 and the electrode pad 200 of thechip 20 and has an opening 220′ for exposing the electrode pad 200.

Referring to FIG. 3B, a first metal layer 21 a′ is formed on theelectrode pad 200 and the dielectric layer 22′ around the electrode pad200 by patterning.

Referring to FIG. 3C, a second metal layer 23 is formed on thedielectric layer 22′ and the first metal layer 21 a.

Then, a conductive pillar 25 is formed on the second metal layer 23corresponding in position to the first metal layer 21 a′ by patterning.The first metal layer 21 a′ has a first distribution-projected area Alarger than the second distribution-projected area S of the conductivepillar 25.

Referring to FIG. 3D, a portion of the second metal layer 23 that is notcovered by the conductive pillar 25 is removed and the remaining portionof the second metal layer 23 covered by the conductive pillar 25 ispreserved, thus obtaining a semiconductor structure. Subsequently, aconductive bump can be formed through a reflow process for electricallyconnecting the semiconductor structure and a packaging substrate. Thesecond metal layer 23 has a third distribution-projected area S′ that isthe same as the second distribution-projected area S of the conductivepillar 25.

The semiconductor structure has a semiconductor chip 20 having at leastan electrode pad 200, a dielectric layer 22 formed on the chip 20 andthe electrode pad 200 and having an opening 220′ for exposing theelectrode pad 200, a first metal layer 21 a′ formed on the electrode pad200 and the dielectric layer 22′ around the electrode pad 200, a secondmetal layer 23 formed on the first metal layer 21 a′, and a conductivepillar 25 disposed on the second metal layer 23. Therein, the firstmetal layer 21 a′ has an area A larger than the sectional area S of theconductive pillar 25. The material of the first metal layer 21 a′ (forexample, titanium) is different from the material of the second metallayer 23 (for example, copper). The semiconductor structure further hasa conductive material 26 disposed on a top surface of the conductivepillar 25.

In the present embodiment, during etching of the second metal layer 23,since the first metal layer 21 a′ has an area A larger than thesectional area S of the conductive pillar 25, even if the first metallayer 21 a′ experiences isotropic etching, the first metal layer 21 a′is still exposed on the dielectric layer 22′, thereby avoiding anundercut as in the prior art so as to provide sufficient support for theconductive pillar 25 and increase the reliability of the conductivebump.

The above-described descriptions of the detailed embodiments areprovided to illustrate the preferred implementation according to thepresent invention, not to limit the scope of the present invention.Accordingly, numerous modifications and variations completed by thosewith ordinary skill in the art will fall within the scope of presentinvention as defined by the appended claims.

1-13. (canceled)
 14. A fabrication method of a semiconductor structure,comprising the steps of: providing a chip having at least an electrodepad; forming a first metal layer on the electrode pad; forming adielectric layer on the chip and the first metal layer, the dielectriclayer having an opening for exposing a portion of the first metal layer;forming a second metal layer on the dielectric layer and the exposedportion of the first metal layer, the first metal layer being differentin material from the second metal layer; forming a conductive pillar onthe second metal layer corresponding in position to the first metallayer; and removing a portion of the second metal layer that is notcovered by the conductive pillar and preserving the remaining portion ofthe second metal layer covered by the conductive pillar.
 15. The methodof claim 14, wherein the first metal layer is a titanium layer or atitanium tungsten layer.
 16. The method of claim 14, wherein forming thefirst metal layer comprises: forming a first metal material on theelectrode pad and a surface of the chip; forming a resist layer to covera portion of the first metal material located on the electrode pad andthe surface of the chip around the electrode pad; removing the remainingportion of the first metal material that is not covered by the resistlayer; and removing the resist layer.
 17. The method of claim 14,wherein the second metal layer is a copper layer.
 18. The method ofclaim 14, wherein the conductive pillar is a copper pillar.
 19. Themethod of claim 14, further comprising, before removing the portion ofthe second metal layer that is not covered by the conductive pillar,forming a conductive material on a top surface of the conductive pillar.20. A fabrication method of a semiconductor structure, comprising:providing a chip having at least an electrode pad; forming a first metallayer on the electrode pad; forming a second metal layer on the firstmetal layer, the first metal layer being different in material from thesecond metal layer; forming a conductive pillar on the second metallayer corresponding in position to the first metal layer, the firstmetal layer having an area larger than a sectional area of theconductive pillar; and removing a portion of the second metal layer thatis not covered by the conductive pillar and preserving the remainingportion of the second metal layer covered by the conductive pillar. 21.The method of claim 20, wherein the first metal layer is a titaniumlayer or a titanium tungsten layer.
 22. The method of claim 20, furthercomprising, before forming the first metal layer on the electrode pad,forming a dielectric layer on the chip and the electrode pad, thedielectric layer having an opening for exposing the electrode pad. 23.The method of claim 22, wherein the first metal layer is further formedon a surface of the dielectric layer around the electrode pad.
 24. Themethod of claim 22, wherein forming the first metal layer comprises:forming a first metal material on the electrode pad and the dielectriclayer; forming a resist layer to cover a portion of the first metalmaterial located on the electrode pad and a surface of the chip aroundthe electrode pad; removing the remaining portion of the first metalmaterial that is not covered by the resist layer; and removing theresist layer.
 25. The method of claim 22, wherein the second metal layeris further formed on the dielectric layer.
 26. The method of claim 20,wherein the second metal layer is a copper layer.
 27. The method ofclaim 20, wherein the conductive pillar is a copper pillar.
 28. Themethod of claim 20, further comprising, before removing the portion ofthe second metal layer that is not covered by the conductive pillar,forming a conductive material on a top surface of the conductive pillar.